1. Field of the Invention
The invention generally relates to failure detection and correction mechanisms for an integrated circuit (IC), and more particularly to emulation of random failures within a memory core of an IC.
2. Prior Art
Failure detection and correction mechanisms that are integrated within an integrated circuit (IC) aim to deal with malfunctions that randomly appear during a device's life time. Since such failure occurs randomly there is no direct way to test that the embedded detection and correction mechanisms work as expected on silicon. It would therefore be advantageous to provide a solution for emulation of such failure mechanism that would enable to ensure proper operation of a device or at least timely detection of a failure. This is of particular importance within embedded memory units commonly used in today's small and large devices.